About Me
I am a final-year Ph.D. candidate in the ECE department, Princeton University. I am supervised by Prof. David Wentzlaff who leads the Princeton Parallel Group.
I am interested in all aspects of computer architecture, especially heterogeneous and reconfigurable architectures for both high-performance and low-power applications. I am also interested in the VLSI design methodology and software programming model for these architectures. I enjoy building chips so as to validate and evaluate my ideas with high fidelity. I am also an advocator of open-source hardware/research as they increase research credibility/reproducibility and encourage community-wide collaboration.
I am on the job market this year. You can find my latest CV here.
Projects
PRGA - Princeton Reconfigurable Gate Array
A silicon-proven, open-source project for generating customized, synthesizable FPGA with complementary, RTL-to-bitstream CAD toolchain.
DOI PDF GitHub Documentation
Duet - Harmonious CPU-FPGA Integration
A novel approach to integrate manycores and multiple eFPGA fabrics to exploit fine-grained acceleration opportunities in the broad application domain.
- Paper accepted to HPCA'23!
- arXiv preprint coming soon!
gem5 x Duet
A gem5 extension for simulating tightly-integrated, ASIC or FPGA-based accelerators. Gem5-Duet achieves C/C++-level simulation speed with cycle-level accuracy by compiling the High-Level Synthesis (HLS) source code into the simulator and applying post-HLS timing annotation in the runtime configuration script.
- In use by researchers at Princeton and UCSC
CIFER
An open-source, heterogeneous, cache-coherent, manycore-eFPGA SoC. CIFER integrates OS-capable cores, parallel tiny core clusters, and eFPGA fabrics in a coherent cache system, covering both ends of the parallelization-specialization spectrum.
- In collab with Prof. Christopher Batten's group
- Prototype chip fabricated and tested
- Paper under review
DECADES
A heterogeneous, cache-coherent SoC with processors, specialized accelerators, intelligent storage units, and eFPGAs. The project is part of an effort to create hardware and software that can be reconfigured on the fly to accelerate important applications.
- In collab with Prof. Margaret Martonosi's group
- In collab with Prof. Luca Carloni's group
- Prototype chip fabricated and tested
- Paper under review
ORDER
ORDER is a microcontroller-eFPGA SoC designed with fully open-source hardware projects (Caravel and PRGA), PDK (SkyWater130), and EDA toolchain (OpenROAD).
- Selected for OpenMPW-6. Fabrication in progress.
Referred Publications (Full List)
Conference Publications
To Appear
Duet: Creating Harmony between Processors and Embedded FPGAs
The 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA-29), Feb-Mar 2023, Montreal, QC, Canada
PRGA: An Open-Source FPGA Research and Prototyping Framework
The 29th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA-29), Feb-Mar 2021, Virtual
Automated Design of FPGAs Facilitated by Cycle-Free Routing
The 30th International Conference on Field-Programmable Logic and Applications (FPL-30), Aug-Sep 2020, Virtual
Journal Publications
Workshops and Posters
Poster
Cycle-Free FPGA Routing Graphs
The 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA-28), Feb 2020, Seaside, California, USA
Workshop
Teaching
- Teaching Assistant, ECE 462/562 (also COS 462), Design of Very Large-Scale Integrated (VLSI) Systems, 2022 Fall
- Mentor, Google Summer of Code, PRGA + FASM: Open-Source Bitgen for FPGAs, 2020 Summer
- Teaching Assistant, ECE 475/575 (also COS 475), Computer Architecture, 2018 Fall
- Co-Advisory of Undergraduate Research
- Jaebyoek Yoon, Architecture and Physical Design of Specialized FPGAs
- Marlon Escobar, CPU-FPGA Integration
- Kevin Liu, Creating Multimode Logic Elements for a Reconfigurable Gate Array