I am officially joining the Department of Electrical and Computer Engineering at the University of Washington (UW ECE) as an assistant professor in 2023 fall! Super excited for the journey ahead!

About Me

I am a final-year Ph.D. candidate in the ECE department, Princeton University. I am supervised by Prof. David Wentzlaff who leads the Princeton Parallel Group.

I am interested in all aspects of computer architecture and digital VLSI design, especially heterogeneous and reconfigurable systems for both high-performance and low-power applications. I enjoy building chips so as to validate and evaluate my ideas with high fidelity. I am also an advocate of open-source hardware/research as they increase research credibility/reproducibility and encourage community-wide collaboration.

Latest News


PRGA - Princeton Reconfigurable Gate Array

A silicon-proven, open-source project for generating customized, synthesizable FPGA with complementary, RTL-to-bitstream CAD toolchain.

  • PRGA has been published and presented at FPGA'21!
  • Cycle-free FPGA has been published and presented at FPL'20!
  • PRGA has been used in three silicon prototypes: CIFER, DECADES, and ORDER. CIFER and DECADES have been tested and functional in our lab!

DOI PDF GitHub Website

Duet - Harmonious CPU-FPGA Integration

A novel approach to integrate manycores and multiple eFPGA fabrics to exploit fine-grained acceleration opportunities in the broad application domain.

arXiv DOI PDF GitHub

gem5 x Duet

A gem5 extension for simulating tightly-integrated, ASIC or FPGA-based accelerators. Gem5-Duet achieves C/C++-level simulation speed with cycle-level accuracy by compiling the High-Level Synthesis (HLS) source code into the simulator and applying post-HLS timing annotation in the runtime configuration script.

  • In use by researchers at Princeton and UCSC
  • Redwood, a research project using gem5-Duet has been published and presented at ISPASS'23!



A heterogeneous, cache-coherent, manycore-eFPGA SoC. CIFER integrates OS-capable cores, parallel tiny core clusters, and eFPGA fabrics in a coherent cache system, covering both ends of the parallelization-specialization spectrum.



A heterogeneous, cache-coherent SoC with processors, specialized accelerators, intelligent storage units, and eFPGAs. The project is part of an effort to create hardware and software that can be reconfigured on the fly to accelerate important applications.

PDF Website


ORDER is a microcontroller-eFPGA SoC designed with fully open-source hardware projects (Caravel and PRGA), PDK (SkyWater130), and EDA toolchain (OpenROAD).

  • Selected for OpenMPW-6. Fabrication in progress.

GitHub Efabless Project

Referred Publications | Full List

ISPASS'23 Conference

Redwood: Flexible and Portable Heterogeneous Tree Traversal Workloads

Yanwen Xu, Ang Li, Tyler Sorensen

2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2023, Raleigh, NC, USA

CICC'23 Conference

CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2, 1.92 MOPS/LUT, Fully Synthesizable, Cache-Coherent, Embedded FPGA

Ting-Jung Chang, Ang Li (Equal Contribution), Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul J. Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff

2023 IEEE Custom Integrated Circuits Conference (CICC), April 2023, San Antonio, TX, USA

CICC'23 Conference

DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET

Fei Gao, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca Carloni, David Wentzlaff

2023 IEEE Custom Integrated Circuits Conference (CICC), April 2023, San Antonio, TX, USA

HPCA'23 Conference

Duet: Creating Harmony between Processors and Embedded FPGAs

Ang Li, August Ning, David Wentzlaff

The 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Feb-Mar 2023, Montreal, QC, Canada

FPGA'21 Conference

PRGA: An Open-Source FPGA Research and Prototyping Framework

Ang Li, David Wentzlaff

The 29th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Feb-Mar 2021, Virtual

FPL'20 Conference

Automated Design of FPGAs Facilitated by Cycle-Free Routing

Ang Li, Ting-Jung Chang, David Wentzlaff

The 30th International Conference on Field-Programmable Logic and Applications (FPL), Aug-Sep 2020, Virtual


  • Teaching Assistant, ECE 462/562 (also COS 462), Design of Very Large-Scale Integrated (VLSI) Systems, 2022 Fall
  • Teaching Assistant, ECE 475/575 (also COS 475), Computer Architecture, 2018 Fall
  • FOSSi Mentor, Google Summer of Code, 2020 Summer
    • Ansh Puvvada, Automating hardware and bitstream verification for PRGA with cocotb
  • Co-Advisory of Undergraduate Research
    • Jaebyoek Yoon, Architecture and Physical Design of Specialized FPGAs
    • Marlon Escobar, CPU-FPGA Integration
    • Kevin Liu, Creating Multimode Logic Elements for a Reconfigurable Gate Array